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HN58X2532IAG HN58X2564IAG
Serial Peripheral Interface 32k EEPROM (4-kword x 8-bit) 64k EEPROM (8-kword x 8-bit) Electrically Erasable and Programmable Read Only Memory
REJ03C0306-0100 Rev.1.00 Nov.16.2006
Description
HN58X25xxx Series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 32-byte page programming function to make it's write operation faster.
Features
* Single supply: 1.8 V to 5.5 V * Serial Peripheral Interface compatible (SPI bus) SPI mode 0 (0,0), 3 (1,1) * Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V) * Power dissipation: Standby: 3 A (max) Active (Read): 3.0 mA (max) Active (Write): 3.5 mA (max) * Automatic page write: 32-byte/page * Write cycle time: 5 ms (2.5 V min), 8 ms (1.8 V min) * Endurance: 106 Erase/Write Cycles * Data retention: 10 Years * Small size packages: SOP-8pin, TSSOP-8pin * Shipping tape and reel TSSOP-8pin : 3,000 IC/reel SOP-8pin : 2,500 IC/reel * Temperature range: -40 to +85C * Lead free product.
Rev.1.00, Nov.16.2006, page 1 of 20
HN58X2532IAG/HN58X2564IAG
Ordering Information
Type No. HN58X2532FPIAG HN58X2564FPIAG HN58X2532TIAG HN58X2564TIAG Internal organization 32-kbit (4096 x 8-bit) 64-kbit (8192 x 8-bit) 32-kbit (4096 x 8-bit) 64-kbit (8192 x 8-bit) 1.8 V to 5.5 V Operating voltage 1.8 V to 5.5 V Frequency 5 MHz (2.5 V to 5.5 V) 3 MHz (1.8 V to 5.5V) 5 MHz (2.5 V to 5.5 V) 3 MHz (1.8 V to 5.5 V) Package 150mil 8-pin plastic SOP PRSP0008DF-B (FP-8DBV) Lead free 8-pin plastic TSSOP PTSP0008JC-B (TTP-8DAV) Lead free
Pin Arrangement
8-pin SOP/TSSOP
S Q W VSS 1 2 3 4 8 7 6 5 VCC HOLD C D
(Top view)
Pin Description
Pin name C D Q S W HOLD VCC VSS Function Serial clock Serial data input Serial data output Chip select Write protect Hold Supply voltage Ground
Rev.1.00, Nov.16.2006, page 2 of 20
HN58X2532IAG/HN58X2564IAG
Block Diagram
High voltage generator VCC VSS
Address generator
X decoder
W C HOLD D Q
Control logic
S
Memory array
Y decoder
Y-select & Sense amp.
Serial-parallel converter
Absolute Maximum Ratings
Parameter Symbol Supply voltage relative to VSS VCC Input voltage relative to VSS VIN Operating temperature range*1 Topr Storage temperature range Tstg Notes: 1. Including electrical characteristics and data retention. 2. VIN (min): -3.0 V for pulse width 50 ns. 3. Should not exceed VCC + 1.0 V. Value -0.6 to + 7.0 -0.5*2 to +7.0*3 -40 to +85 -65 to +125 Unit V V C C
DC Operating Conditions
Parameter Supply voltage Input voltage Operating temperature range Symbol VCC VSS VIH VIL Topr Min 1.8 0 VCC x 0.7 -0.3*1 -40 Typ 0 Max 5.5 0 VCC + 0.5*2 VCC x 0.3 +85 Unit V V V V C
Notes: 1. VIN (min): -1.0 V for pulse width 50 ns. 2. VIN (max): VCC + 1.0 V for pulse width 50 ns.
Rev.1.00, Nov.16.2006, page 3 of 20
HN58X2532IAG/HN58X2564IAG
DC Characteristics
Parameter Input leakage current Output leakage current VCC current Standby Active Symbol ILI ILO ISB ICC1 Min Max 2 2 3 2 Unit A A A mA Test conditions VCC = 5.5 V, VIN = 0 to 5.5 V (S, D, C, HOLD, W) VCC = 5.5 V, VOUT = 0 to 5.5 V (Q) VIN = VSS or VCC, VCC = 5.5 V VCC = 3.6 V, Read at 5 MHz VIN = VCC x 0.1/VCC x 0.9 Q = OPEN VCC = 5.5 V, Read at 5 MHz VIN = VCC x 0.1/VCC x 0.9 Q = OPEN VCC = 3.6 V, Write at 5 MHz VIN = VCC x 0.1/VCC x 0.9 VCC = 5.5 V, Write at 5 MHz VIN = VCC x 0.1/VCC x 0.9 VCC = 5.5 V, IOL = 2 mA VCC = 2.5 V, IOL = 1.5 mA VCC = 5.5 V, IOL = -2 mA VCC = 2.5 V, IOL = -0.4 mA
3
mA
ICC2

2 3.5 0.4 0.4
mA mA V V V V
Output voltage
VOL1 VOL2 VOH1 VOH2
VCC x 0.8 VCC x 0.8
Rev.1.00, Nov.16.2006, page 4 of 20
HN58X2532IAG/HN58X2564IAG
AC Characteristics
Test Conditions * Input pules levels: VIL = VCC x 0.2 VIH = VCC x 0.8 * Input rise and fall time: 10 ns * Input and output timing reference levels: VCC x 0.3, VCC x 0.7 * Output reference levels: VCC x 0.5 * Output load: 100 pF
Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock high setup time before HOLD active Clock high setup time before HOLD not active Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL tCLCH tCHCL tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH Alt fSCK tCSS1 tCSS2 tCS tCSH tCLH tCLL tRC tFC tDSU tDH Min 90 90 90 90 90 90 90 20 30 70 40 60 60
(Ta = -40 to +85C, VCC = 2.5 V to 5.5 V)
Max 5 1 1 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms cycles Notes
1 1 2 2
Output disable time tSHQZ tDIS 100 Clock low to output valid tCLQV tV 70 Output hold time tCLQX tHO 0 Output rise time tQLQH tRO 50 Output fall time tQHQL tFO 50 HOLD high to output low-Z tHHQX tLZ 50 HOLD low to output high-Z tHLQZ tHZ 100 Write time tW tWC 5 Erase / Write Endurance 106 Notes: 1. tCH + tCL 1/fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Value guaranteed by characterization, not 100% tested in products (Ta = 25C).
2
2 2 2 2 3
Rev.1.00, Nov.16.2006, page 5 of 20
HN58X2532IAG/HN58X2564IAG (Ta = -40 to +85C, VCC = 1.8 V to 5.5 V)
Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock high setup time before HOLD active Clock high setup time before HOLD not active Output disable time Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL tCLCH tCHCL tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ Alt fSCK tCSS1 tCSS2 tCS tCSH tCLH tCLL tRC tFC tDSU tDH tDIS Min 100 100 150 100 100 150 150 30 50 140 90 120 120 Max 3 1 1 -- 200 Unit MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms cycles Notes
1 1 2 2
2
Clock low to output valid tCLQV tV 120 Output hold time tCLQX tHO 0 Output rise time tQLQH tRO 100 Output fall time tQHQL tFO 100 HOLD high to output low-Z tHHQX tLZ 100 HOLD low to output high-Z tHLQZ tHZ 100 Write time tW tWC 8 Erase / Write Endurance 106 Notes: 1. tCH + tCL 1/fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Value guaranteed by characterization, not 100% tested in products (Ta = 25C).
2 2 2 2 3
Rev.1.00, Nov.16.2006, page 6 of 20
HN58X2532IAG/HN58X2564IAG
Timing Waveforms
Serial Input Timing
tSHSL
S
tCHSL tSLCH tCHSH
tSHCH
C
tDVCH tCHDX tCLCH LSB IN tCHCL
D
MSB IN
Q
High Impedance
Hold Timing
S
tHLCH tHHCH
tCHHL
C
tCHHH
D
tHLQZ tHHQX
Q HOLD
Output Timing
S
tCH tSHQZ
C
tCL
D
ADDR LSB IN
tCLQV tCLQX
tCLQX
tCLQV
Q
LSB OUT
tQLQH tQHQL
Rev.1.00, Nov.16.2006, page 7 of 20
HN58X2532IAG/HN58X2564IAG
Pin Function
Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (C). Serial data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of serial clock (C). Serial clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after the falling edge of serial clock (C). Chip select (S) When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. Unless an internal write cycle is in progress, the device will be in the standby mode. Driving chip select (S) low enables the device, placing it in the active power mode. After power-up, a falling edge on chip select (S) is required prior to the start of any instruction. Hold (HOLD) The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C) are don't care. To start the hold condition, the device must be selected, with chip select (S) driven low. Write protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the BP1 and BP0 bits of the status register). This pin must be driven either high or low, and must be stable during all write operations.
Rev.1.00, Nov.16.2006, page 8 of 20
HN58X2532IAG/HN58X2564IAG
Functional Description
Status Register The following figure shows the Status Register Format. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. Status Register Format
b7
SRWD 0 0 0 BP1 BP0 WEL
b0
WIP
Status Register Write Disable Block Protect Bits Write Enable Latch Bits Write In Progress Bits
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.
Instructions Each instruction starts with a single-byte code, as summarized in the following table. If an invalid instruction is sent (one not contained in the following table), the device automatically deselects itself. Instruction Set
Instruction WREN WRDI RDSR WRSR READ WRITE Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction Format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Rev.1.00, Nov.16.2006, page 9 of 20
HN58X2532IAG/HN58X2564IAG Write Enable (WREN): The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. Write Enable (WREN) Sequence
S
VIH VIL
W
VIH VIL 0 1 2 3 4 5 6 7
C
VIH VIL Instruction
VIH
D
VIL
Q
High-Z
Rev.1.00, Nov.16.2006, page 10 of 20
HN58X2532IAG/HN58X2564IAG Write Disable (WRDI): One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion
Write Disable (WRDI) Sequence
S
VIH VIL
W
VIH VIL 0 1 2 3 4 5 6 7
C
VIH VIL Instruction
VIH
D
VIL
Q
High-Z
Rev.1.00, Nov.16.2006, page 11 of 20
HN58X2532IAG/HN58X2564IAG Read Status Register (RDSR): The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in the following figure. Read Status Register (RDSR) Sequence
S
VIH VIL
W
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
VIH VIL
VIH
D
VIL Status Register Out
Q
High-Z 7 6 5 4 3 2 1 0 7
The status and control bits of the Status Register are as follows: WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write or Write Status Register instructions are accepted. BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as defined in the Status Register Format table) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allows the device to be put in the Hardware Protected mode (When the Status Register Write Disable (SRWD) bit is set to 1, and write protect (W) signal is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Rev.1.00, Nov.16.2006, page 12 of 20
HN58X2532IAG/HN58X2564IAG Write Status Register (WRSR): The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch(WEL). The instruction sequence is shown in the following figure. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip select (S) must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as chip select (S) is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in the Status Register Format table. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the write protect (W) signal. The Status Register Write Disable (SRWD) bit and write protect (W) signal allows the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values just before the start of the execution of the Write Status Register (WRSR) instruction. The new, updated values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction. Write Status Register (WRSR) Sequence
S
VIH VIL
W
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
VIH VIL Status Register In VIH 7 MSB 6 5 4 3 2 1 0
D
VIL
Q
High-Z
Rev.1.00, Nov.16.2006, page 13 of 20
HN58X2532IAG/HN58X2564IAG Read from Memory Array (READ): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (Q). If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Read from Memory Array (READ) Sequence
S
VIH VIL
W
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
VIH VIL
Instruction
16-Bit Address
VIH
D
A15 A14 A13
A3 A2 A1
A0
VIL Data Out 1 Data Out 2
2 1 0
7
Q
High-Z
7
6
5
4
3
Note:
1. Depending on the memory size, as shown in the following table, the most significant address bits are don't care.
Address Range Bits
Device HN58X2564IAG Address bits A12 to A0 Notes: 1. b15-b13 are don't care on the HN58X2564IAG 2. b15-b12 are don't care on the HN58X2532IAG HN58X2532IAG A11 to A0
Rev.1.00, Nov.16.2006, page 14 of 20
HN58X2532IAG/HN58X2564IAG Write to Memory Array (WRITE): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D). The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in AC Characteristics). At the end of the cycle, the Write In Progress (WIP) bit is reset to 0. If, though, chip select (S) continues to be driven low, as shown in the following figure, the next byte of the input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these device is 32 bytes). The instruction is not accepted, and is not executed, under the following conditions: If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) If a Write cycle is already in progress If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. Byte Write (WRITE) Sequence (1 Byte)
S
VIH VIL
W
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
VIH VIL
Instruction
16-Bit Address
Data Byte 1
1
VIH
D
15 14 13
3
2
0
7
6
5
4
3
2
1
0
VIL
Q
High-Z
Note:
1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bits are don't care.
Rev.1.00, Nov.16.2006, page 15 of 20
HN58X2532IAG/HN58X2564IAG Byte Write (WRITE) Sequence (Page)
S
VIH VIL
W
VIH VIL 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
VIH VIL
Instruction VIH
16-Bit Address
Data Byte 1 1 0 7 6 5 4 3 2 1 0
D
15 14 13
3
2
VIL
Q
High-Z
S
VIH VIL
W
VIH VIL 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
VIH VIL
Data Byte 2
Data Byte 3
Data Byte N 1 0 6 5 4 3 2 1 0
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
Q
High-Z
Note:
1. Depending on the memory size, as shown in Address Range Bits table, the most significant address bits are don't care.
Rev.1.00, Nov.16.2006, page 16 of 20
HN58X2532IAG/HN58X2564IAG
Data Protect
The protection features of the device are summarized in the following table. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless weather write protect (W) is driven high or low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of write protect (W): If write protect (W) is driven high, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If write protect (W) is driven low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: By setting the Status Register Write Disable (SRWD) bit after driving write protect (W) low. By driving write protect (W) low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect (W) high. If write protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
Write Protected Block Size
Status register bits BP1 BP0 0 1 0 1 Protected blocks None Upper quarter Upper half Whole memory Array addresses protected HN58X2564IAG HN58X2532IAG None None 1800h - 1FFFh 0C00h - 0FFFh 1000h - 1FFFh 0800h - 0FFFh 0000h - 1FFFh 0000h - 0FFFh
0 0 1 1
Protection Modes
W signal 1 0 Write protection of the status register Memory protect Protected area*1 Unprotected area*1 Ready to accept Write instructions
SRWD bit
Mode
Software Status register is writable Write protected protected (SPM) (if the WREN) instruction has set the WEL bit). The values in the BP1 and BP0 bits can be changed.
0 1 0
0 1 1 Write protected Hardware Status register is protected (HPM) hardware write protected. The values in the BP1 and BP0 bits cannot be changed. Ready to accept Write instructions
Note:
1. As defined by the values in the Block Protected (BP1, BP0) bits of the Status Register, as shown in the former table.
Rev.1.00, Nov.16.2006, page 17 of 20
HN58X2532IAG/HN58X2564IAG
Hold Condition
The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C) are don't care. To enter the hold condition, the device must be selected, with chip select (S) low. Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The hold condition starts when the hold (HOLD) signal is driven low at the same time as serial clock (C) already being low (as shown in the following figure). The hold condition ends when the hold (HOLD) signal is driven high at the same time as serial clock (C) already being low. The following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock (C) being low. Hold Condition Activation
HOLD status
HOLD status
C HOLD
Notes
Data Protection at VCC On/Off When VCC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. * S should be fixed to VCC during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. * VCC should be turned on/off after the EEPROM is placed in a standby state. * VCC should be turned on from the ground level (VSS) in order for the EEPROM not to enter the unintentional programming mode. * VCC turn on speed should be slower than 10 s/V. * When WRSR or WRITE instruction is executed before VCC turns off, VCC should be turned off after waiting write cycle time (tW).
Rev.1.00, Nov.16.2006, page 18 of 20
HN58X2532IAG/HN58X2564IAG
Package Dimensions
HN58X2532FPIAG/HN58X2564FPIAG (PRSP0008DF-B / Previous Code: FP-8DBV)
JEITA Package Code P-SOP8-3.9x4.89-1.27 RENESAS Code PRSP0008DF-B Previous Code FP-8DBV MASS[Typ.] 0.08g
*1
D
F 5
8
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1
Z
e
c
4
*3
Reference Symbol
Dimension in Millimeters
bp
x
M
L1
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 4.89 5.15 3.90 0.102 0.14 0.254 1.73 0.35 0.40 0.45 0.15 0.20 0.25 0 8 5.84 6.02 6.20 1.27 0.25 0.10 0.69 0.406 0.60 0.889 1.06
Rev.1.00, Nov.16.2006, page 19 of 20
A
HN58X2532IAG/HN58X2564IAG HN58X2532TIAG/HN58X2564TIAG (PTSP0008JC-B / Previous Code: TTP-8DAV)
JEITA Package Code P-TSSOP8-4.4x3-0.65 RENESAS Code PTSP0008JC-B Previous Code TTP-8DAV MASS[Typ.] 0.034g
*1
D
F 5
8
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
*2
Terminal cross section ( Ni/Pd/Au plating )
Index mark
c
Reference Symbol
Dimension in Millimeters
L1
1
Z
e
4
*3
bp
x
M
A
A1
L
Detail F
y
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 3.00 3.30 4.40 0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0 8 6.20 6.40 6.60 0.65 0.13 0.10 0.805 0.40 0.50 0.60 1.00
Rev.1.00, Nov.16.2006, page 20 of 20
Revision History
HN58X2532IAG/HN58X2564IAG Data Sheet
Contents of Modification Description
Rev. 1.00
Date Nov. 16, 2006 Page Initial issue
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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